ProTiming - Prolific's block-level optimization tool

ProTiming

“Companies routinely analyze critical paths and insert additional cells by hand to achieve better timing. ProTiming simply automates this process.”

ProTiming™ is Prolific's block-level optimization tool, working in the synthesis and place-and-route (SPR) flow. ProTiming gives IC designers up to 20% improvement in timing and power, with or without adding new cells to the standard cell library. ProTiming performs design-specific timing optimization during the static timing analysis step of the physical design flow. The software makes use of cells already existing in the library and can provide a 5-10% performance increase without modifying RTL or adding new cells to the library. If desired, ProTiming can also specify new cells that are created as needed, either by traditional methods or automatically by Prolific's ProGenesis tool suite, for an additional 5-10% performance increase.

The static library size of a typical SPR flow limits optimization, making the resulting layout less efficient than full-custom design. Allowing cell optimization to take place within the design flow removes the restrictions of a limited and arbitrary set of library elements, providing several real advantages: performance improvements; time-to-market reduction due to reduced design iterations; and reductions in area and power consumption.

Design	Initial MHz	Final MHz	Timing Gain	Notes
ARM Core	249	283	13.65%	Taped-out design
ARM Core	257	283	10.12%	No new cells
Calculator	1263	1383	9.50%	No new cells
Controller	177	216	22.03%	No new cells
Controller	786	863	9.80%	Taped-out design
Controller	375	414	10.40%	11 new cells
Controller	339	379	11.80%	No new cells
CPU Core	334	400	19.76%	Low power design
CPU Core	134	151	12.69%	Taped-out design
CPU Core	264	293	10.98%	Taped-out design
DSP Core	730	804	10.14%	9 new cells
Graphics	223	245	9.87%	Taped-out design
I/O Block	191	204	6.81%	No new cells
MIPS Core	281	318	13.17%	1.36% instances changed

ProTiming for Low Power and Area

Using ProTiming allows designers to focus on power and relax the timing constraints during SPR. The critical paths can then be addressed during static timing analysis (STA) to regain timing. This will only increase the transistor sizes in the critical paths, allowing the design to meet timing requirements while saving overall power and area. ProTiming also supports a more aggressive approach; ProTiming will replace all cells after STA with low L (low power) or half drive strengths, then fix timing by increasing the drive strengths only in the critical paths required to meet timing. This methodology results in power savings of up to 20% or more.

Features

• Analyzes critical paths down to the standard cells
• Optimizes designs without RTL changes
• Optimizes without using new cells
• Optionally, adds only alternate drive-strength cells
• Fully integrated with Synopsys PrimeTime®

Benefits

• Design-specific performance improvements of 10% or more
• Time-to-market, reduced design iterations
• Supports industry-standard SPR flow
• Low risk, won't compromise design or verification flow