ProGenesis

ProGenesis® is Prolific's netlist-to-layout solution for creating optimized standard cell libraries. Whether cells are synthesized from SPICE input, custom-designed using a sticks graphical editor, produced from a large database of generators, or migrated from existing GDS layout, ProGenesis provides total control over every edge of the layout, captures manual edits, and quickly and automatically regenerates complete libraries. The graphical technology configuration tool and cell template wizards simplify the set-up and cell creation process.

ProGenesis allows creation of usable layout while the design rules, SPICE netlists, and cell architecture are still in flux, because the technical specifications are processed automatically without compromising the validity of the existing layout. This enables designers to consider the architectural impact of different design styles by running characterization or place and route tests on cells created with early versions of the design rules. This eases resource limitations, improves library intelligence and shortens time-to-market. Furthermore, the ProGenesis approach, which combines synthesis, generation, and compaction, ensures design optimization, thus improving performance, area, and power consumption.

 


ProGenesis supports all 1.0 micron to 45nm process design rules, Design For Manufacture (DFM) practices to increase silicon yield and reliability, and sub-wavelength optimization Resolution Enhancement Techniques (RET): Optical Proximity Correction (OPC); Strong and Attenuated Phase-Shift Mask (PSM); Scattering Bars (SB); and Off-Axis Illumination (OAI).

Features

• Transistor Level Synthesis
• True 2D Compaction
• Fast and Predictable Generation Technology
• Sticks Graphical Editor and Tcl Language Interface

 

Benefits

• Produces hand-craft quality layout fast and efficiently
• Rebuild complete libraries without manual intervention after specification changes
• Capture manual layout changes for automatic reuse
• Full support for non-standard processes, design rules, cell templates, transistors, wires, and vias

 

 

 

 

 
 

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