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ProTiming — Block-level Timing
Optimization
• Design-specific performance improvements
of 10% or more
• Reduced design iterations reduce time-to-market
• Use within your industry-standard SPR flow
• Won't compromise design or verification flow
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ProGenesis — Automated
Standard Cell Creation
• Produce hand-drawn quality layout fast
and efficiently
• Rebuild complete libraries without manual intervention
when specifications change
• Capture manual layout changes for automatic reuse
• Use any process, design rules, cell templates, transistors,
wires, and vias
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