NEWARK, Calif. -- January 14, 2003 - Prolific Inc., the leading provider of automated standard cell creation software, today announced that Telairity Semiconductor will use the ProGenesis® software tools to accelerate development of the custom logic and standard cell elements used to build the fundamental design groups utilized in Telairity's unique ASIC flow. Telairity implemented its design groups so that with Prolific's ProGenesis they can harden them across a wide variety of advanced process technologies to suit customer requirements.

Telairity Semiconductor Inc. is a fabless ASIC company that employs its own carefully crafted groups of hardened IP to double the performance realized with traditional ASIC approaches. By providing tools and services with its highly reusable and portable IP, Telairity can decrease customer time to market to as little as one tenth of most ASIC flows. Telairity is developing a broad range of hardened IP groups, initially targeting high performance, low power applications in the communications and consumer markets.

"As we target leading edge process technologies for our customer's complex semiconductor designs, our IP development flow relies on automation provided by our layout and characterization methodology," noted Howard Sachs, president and CEO of Telairity Semiconductor. "We simply must have easy-to-use tools that match our requirements for speed and accuracy. The fully automated capabilities of ProGenesis and the superior technical support offered by Prolific are instrumental to our success."

Prolific's ProGenesis family of tools is the industry standard for automated creation and migration of standard cell libraries. Key to the tools' success is its ability to generate better-than handcrafted quality results in significantly less time than that of other tools or traditional methods.

About Prolific

Founded in 1995, Prolific Inc. develops the leading software for automatically creating standard cells without giving up custom design styles. Prolific's ProGenesis® suite allows designers to quickly and accurately create optimized standard-cell libraries using design-specific information contained in a SPICE netlist, process-specific information defined in design rules, and designer-specific options specified in the cell template. Prolific's ProTiming™ tool integrates the optimization of standard cell libraries into the mainstream EDA flow, enabling design-specific standard cells to be inserted on the fly during the synthesis and place-and-route phase of the EDA design flow. Prolific is headquartered in Newark, Calif., at 39899 Balentine Dr., Suite 380, Newark, CA 94560, telephone 510/252-0490, fax 510/252-0491. For more information, visit www.prolificinc.com.

About Telairity Semiconductor, Inc.

Telairity Semiconductor Inc. is a fabless ASIC company providing tools, methodology, hard IP and services for developing a broad range of products aimed at high performance, low power and fast time to market applications. The initial applications will be targeted for the communications and consumer markets. Telairity s highly reusable and portable IP and methodology decreases time to market by more than 10X over traditional ASIC approaches and increases performance by more than 2X. Founded in April 2001, by Howard Sachs, President and CEO, Telairity is a privately held company headquartered in Santa Clara, Calif. Jim Meadlock, ex-President/CEO and founder of Intergraph Corporation is the Chairman of the Board for Telairity and lead investor. More information about the company, its products and services is available at www.telairity.com or call 408-764-0270 x104 for more information.

ProGenesis is a registered trademark and ProTiming is a trademark of Prolific, Inc. PrimeTime is a registered trademark of Synopsys, Inc. Prolific acknowledges trademarks or registered trademarks of other organizations for their respective products and services.