NEWARK, Calif. -- April 7, 2003 -- Prolific Inc., the leading provider of automated standard cell creation software, today announced the availability of ProTiming™, software for the automatic deployment of standard cells in the mainstream EDA flow. The block-level optimization tool puts IC designers in control of standard cell libraries in the synthesis and place-and-route (SPR) flow. ProTiming performs design-specific optimization and sizing, providing the advantages of full-custom design in a completely automated standard cell design flow. The software can make use of optimized cells already existing in the library, or created as needed, either by traditional methods or automatically by Prolific's ProGenesis® tool suite.

The static library size of a typical SPR flow limits optimization, making the resulting layout less efficient than full-custom design. Allowing cell optimization to take place within the design flow removes the inherent restrictions of using a limited and arbitrary set of library elements, providing several real advantages: performance improvements; time-to-market reduction due to reduced design iterations; and reductions in area and power consumption.

"The ProTiming analysis identifies the new cells to be created and estimates their timing behavior based on existing cells," reported Dave Parker of LSI Logic. "We have independently verified that Prolific's approach for estimating cell timing behavior is sound -- the ProTiming estimates were essentially identical to those generated by our cell characterization flow. The set-up for running ProTiming is straight-forward, requiring input files that are part of our standard development flow (STA script, Verilog, SPEF, constraints, etc.). ProTiming gave a 9.3% performance increase on flop-to-flop delays and 11.9% performance increase on the I/O pins, while increasing the area only 4%"

ProTiming in the SPR Flow

During the static timing analysis step, ProTiming addresses the critical paths of a design block and chooses cells to improve the cycle time while minimizing area and power. Cells not found in the base library are created and inserted into the design via the standard ECO process. These cells are always drive-strength derivatives of the standard library only, never new functions or complex cells, so there is no risk of breaking the integrity of the cell-based design flow and verification methodology. This integrated solution is designed expressly to help the SPR tools find a high-quality solution while limiting the overall number of cells.

ProTiming Features

• Analyzes critical paths down to the standard cells
• Optimizes designs without RTL changes
• Drive-strength derivatives only, no new functions or non-standard cells
• Fully integrated with Synopsys PrimeTime®

ProTiming Benefits

• Design-specific performance improvements of 10% or more
• Time-to-market, reduced design iterations
• Supports industry-standard SPR flow
• Low risk, won't compromise design or verification flow

ProTiming is currently available; for a free evaluation, go to www.prolificinc.com/protiming_trial.html. Pricing is $125,000 for a time-based license. Prolific tools run on HP-UX, Linux, and Solaris platforms.

About Prolific

Prolific Inc.'s IC design optimization software significantly reduces time to tapeout by automatically improving performance or reducing power consumption of cell-based designs. Prolific's customers include companies like AMD, NEC, ARM, and Broadcom. Prolific is a 10-year-old, privately held, profitable company based in Silicon Valley, at 39899 Balentine Dr., Suite 380, Newark, CA 94560, telephone (510) 252-0490, fax (510) 252-0491. For more information, visit http://www.prolificinc.com/.

ProGenesis is a registered trademark and ProTiming is a trademark of Prolific, Inc. PrimeTime is a registered trademark of Synopsys, Inc. Prolific acknowledges trademarks or registered trademarks of other organizations for their respective products and services.