NEWARK, Calif. -- February 24, 2003 - Prolific Inc., the leading provider of automated standard cell generation software, today announced breakthrough technology for standard cell design with the release of its ProGenesis® Design For Manufacture software. Lost yield regularly costs companies millions of dollars per year per production line. ProGenesis DFM addresses the increasing expense incurred as design capabilities in the semiconductor sector outpace manufacturing realities.

DFM has not been seriously targeted during the design process because of the difficulty in predicting a design's manufacturability. Time-to-market and die size can be reliably predicted and calculated before production begins, but yield figures are only available after production is underway. But as manufacturability becomes one of the most important factors in the success of semiconductor products, more design effort and expertise is being focused on DFM. The question is no longer whether manufacturability deserves design consideration, but where in the design process that consideration pays the largest dividends.

Standard cells are critical in achieving a manufacturable design, blending logic design information (netlists), design trade-offs of performance, power, area, and yield (cell architecture), and manufacturing process requirements (design rules). Standard cells are used repeatedly throughout a design, and contribute significantly to the manufacturability of an IC. These factors make standard cells the logical focus of a move to manufacturability.

Indiscriminate adoption of available DFM practices at the standard cell level could result in a design area penalty of 30% or more. Fortunately, blind use of all DFM practices is not necessary. With ProGenesis DFM, standard cell designers have an automated way to analyze DFM options at the cell level and only implement those that do not increase area. Because studies show that 70-80% of the DFM practices can be implemented without an area penalty, the ProGenesis DFM technology offers yield increases in addition to lower mask costs and faster, more reliable silicon.

ProGenesis DFM has addressed more than twenty manufacturing enhancement practices. These include decreasing the likelihood of contact/via failures by increasing contact/via metal overlap, using wider and longer metal end-of-line extensions, and using redundant vias/contacts. The number of critical features can be reduced by limiting poly and diffusion routing, using straight transistors, minimizing the number of vertices, and avoiding forbidden pitches. Optical & Process correction (OPC) and other resolution enhancement technologies (RET) are also a critical aspect of improving manufacturability. Integrating RET-friendly design styles will not only reduce RET layout-processing complexity and mask-making cycle time and cost, it will also ensure best silicon performance. DFM RET recommendations include: Use rectangular line-ends, forbid circle or oval shapes, avoid short-cropped corners, small zig-zag and jogs, and certain pitches.

"Even with the newest High-NA 193nm scanners, the 90nm process node requires much more intense RET methods than ever before," said Leigh Anderson, Calibre RET marketing manager at Mentor Graphics. "The capability of ProGenesis to automate cell generation taking into account the design layout restrictions of a particular RET option fullfills a critical requirement for automated library generation for the 90nm node, and will be even more critical for the follow-on 65nm node. The ProGenesis DFM product is very complementary to Calibre's suite of tools enabling advanced design-to-silicon flows including RET."

"As the industry moves to process technologies of 130 nanometer and below semiconductor design flows require tools that consider manufacturability as well as timing, power and signal integrity," noted Vess Johnson, president and CEO of Silicon Metrics. "As libraries are optimized for manufacturability, accurate characterization and modeling is required to reflect the changes in timing performance, power consumption, and noise sensitivity. Working together, ProGenesis DFM for automated cell generation and SiliconSmart CR for accurate characterization and modeling provide the optimized physical layouts and accurate cell models required for nanometer designs."

About Prolific

Founded in 1995, Prolific Inc. develops the leading software for automatically creating standard cells without giving up custom design styles. Prolific's ProGenesis® suite allows designers to quickly and accurately create optimized standard-cell libraries using design-specific information contained in a SPICE netlist, process-specific information defined in design rules, and designer-specific options specified in the cell template. Prolific's ProTimingT tool integrates the optimization of standard cell libraries into the mainstream EDA flow, enabling cycle time improvements during the synthesis and place-and-route phase of the EDA design flow. Prolific is headquartered in Newark, Calif., at 39899 Balentine Dr., Suite 380, Newark, CA 94560, telephone 510/252-0490, fax 510/252-0491. For more information, visit www.prolificinc.com.

ProGenesis is a registered trademark and ProTiming is a trademark of Prolific, Inc. PrimeTime is a registered trademark of Synopsys, Inc. Prolific acknowledges trademarks or registered trademarks of other organizations for their respective products and services.