Use Your Multi-Vt Library to Minimize Leakage Power

Prolific demonstrates ProPower at DATE 06

NEWARK, Calif. -- February 28, 2006 - Prolific Inc. today announced demonstrations of ProPower™, its final-pass leakage power reduction tool, at the DATE 06 exhibition for electronic design, automation, and test in Europe. Prolific's exhibit, A19, is located in Hall B0. Leakage power, which is becoming a more widespread probleem as semiconductor device manufacturers move to fabrication processes with smaller features, cause integrated circuits (ICs) to consume power even when they are not in use. This has a tremendous impact on the battery life of portable electronics.

ProPower focuses on a specific, effective method for reducing power leakage in a completed IC design: design-specific Vt swapping during the static timing analysis step of the physical design flow. The software makes use of cells already existing in any multi-Vt library, producing an average of 15% leakage power reduction, even after other tools have been use to reduce power leakage. These benefits do not require modifying RTL, adding cells to the library, or even an ECO through the place-and-route flow. Furthermore, because ProPower runs as a plug-in to Prolific's ProTiming performance optimization tool, the solution does not change the total net slack (TNS) or worst net slack (WNS) for the design. Performance measurement is performed by Synopsys' PrimeTime, so no correlation to a third-party timing engine is required.

ProPower runs on HP-UX, Linux, and Sun Solaris platforms as an add-on to Prolific's popular ProTiming product.

About Prolific

Founded in 1995, Prolific Inc. develops the leading software for automatically creating standard cells without giving up custom design styles. Prolific's ProGenesis® suite allows designers to quickly and accurately create optimized standard-cell libraries using design-specific information contained in a SPICE netlist, process-specific information defined in design rules, and designer-specific options specified in the cell template. Prolific's ProTiming™ tool integrates the optimization of standard cell libraries into the mainstream EDA flow, enabling design-specific standard cells to be inserted on the fly during the synthesis and place-and-route phase of the EDA design flow. Prolific is headquartered in Newark, Calif., at 39899 Balentine Dr., Suite 380, Newark, CA 94560, telephone 510/252-0490, fax 510/252-0491. For more information, visit www.prolificinc.com.



ProTiming and ProPower are trademarks of Prolific, Inc. PrimeTime is a registered trademark of Synopsys, Inc. Prolific acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

 

 
 

2000-2006 Prolific. All rights reserved.